`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:21:17 04/01/2014
// Design Name:   scores_dec
// Module Name:   X:/EC551_project/logic/t_score.v
// Project Name:  logic
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: scores_dec
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module t_score;

	// Inputs
	reg [15:0] scores;

	// Outputs
	wire [3:0] a;
	wire [3:0] b;
	wire [3:0] c;
	wire [3:0] d;

	// Instantiate the Unit Under Test (UUT)
	scores_dec uut (
		.scores(scores), 
		.a(a), 
		.b(b), 
		.c(c), 
		.d(d)
	);

	initial begin
		// Initialize Inputs
		scores = 15;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

